The present invention relates to a semiconductor fabricating technique, and more particularly, to a method for doping polysilicon and a method for fabricating a dual poly gate using the same.
It is well known that dual poly gates operate in a peripheral circuit of a dynamic random access memory (DRAM). Each dual poly gate includes an N-type polysilicon as a gate of an NMOS transistor and a P-type polysilicon as a gate of a PMOS transistor. If a gate of a PMOS transistor is formed of a P-type polysilicon unlike a typical structure where all the gates of NMOS and PMOS transistors are formed of an N-type polysilicon, a short channel effect is reduced, and also a drain saturation current Idsat, a sub threshold voltage, and a drain induced barrier lowering (DIBL) are improved with respect to the same threshold voltage Vt. Furthermore, a DRAM device can be fabricated with improved data retention time, low power consumption and high performance.
When applying a dual poly gate, if a cell region is formed of a recess gate, an N-type impurity needs to be uniformly doped into a gate polysilicon of an NMOS transistor at the cell region. When forming gates of NMOS and PMOS transistors constituting a device, a counter doping process is performed. After forming an N-type polysilicon, the counter doping process converts the N-type polysilicon into a P-type polysilicon by doping a P-type impurity into only the N-type polysilicon of a gate of the PMOS transistor.
While applying this counter doping process, a doping concentration of an impurity should be at least approximately 4.0×1020 atms/cm3. However, if high-doping of a high concentration is applied using a typical beam-line implant, there may be limitations in mass production. Accordingly, plasma doping is used for impurity doping such that a P-type polysilicon is formed.
However, when the plasma doping utilizes plasma enhanced chemical vapor deposition (PECVD), a by-product deposition layer is formed over polysilicon during the doping of an impurity and a profile is formed where most of the dopant is doped on the surface of the polysilicon. Accordingly, the dopant loss of approximately 70% to approximately 80% occurs due to the removing and cleaning processes of an ion implantation barrier for the impurity doping. Because most of the dopant is doped on the surface of the polysilicon, even after a subsequent thermal annealing, inter-diffusion in a polysilicon layer is less than expected when considering the beam line implant. Therefore, an impurity concentration on the interface between the polysilicon and a gate oxide layer is low and, according thereto, electrical characteristics of a device become deteriorated.
FIG. 1 illustrates a graph for comparing beamline implant with plasma doping.
Referring to FIG. 1, after performing impurity doping through the beamline implant and the plasma doping a boron concentration by the plasma doping is more highly concentrated near the surface compared to the beamline implant.
Furthermore, in a case of the beamline implant, the boron concentration is uniform only up to a predetermined depth, but in a case of the plasma doping, the boron concentration is concentrated near the surface and its concentration is decreased drastically as it approaches the bottom. The dopant concentrated near the surface is removed by a subsequent cleansing process, and therefore, inter-diffusion becomes less when a subsequent impurity is activated. Accordingly, electrical characteristics of a device become deteriorated.
FIG. 2 illustrates a transmission electron microscope (TEM) picture after plasma doping.
Referring to FIG. 2, a by-product deposition layer is formed over polysilicon. Due to the characteristics of plasma doping, the by-product deposition layer is formed on the surface of the polysilicon, and most of the dopant that is doped during the plasma doping is included in the by-product deposition layer. The by-product deposition layer is removed by a subsequent cleansing process and according thereto, dopant loss of approximately 70% to approximately 80% occurs.